1. FIELD OF THE INVENTION
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for controlling a plating process.
2. DESCRIPTION OF THE RELATED ART
A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e.g., transistors, formed above the surface of a semi-conductive substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnect structures. Many modem integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnect structures must be made in multiple layers to conserve plot space on the semiconductive substrate.
The conductive interconnect structures are typically accomplished through the formation of a plurality of conductive lines and conductive plugs, commonly referred to as contacts or vias, formed in alternative layers of dielectric materials formed on the device. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. For certain types of interconnect structures, such as those formed using copper, the conductive lines that connect the various interconnect structures are commonly formed in trenches defined in the dielectric layers.
A contact is generally used to define an interconnect structure (e.g., comprised of polysilicon or metal) to an underlying polysilicon layer (e.g., source/drain or gate region of a transistor), while a via denotes a metal to metal interconnect structure. For contacts and vias, a contact opening is formed in an insulating layer overlying the conductive member. A second conductive layer is then formed over the contact opening and electrical communication is established with the conductive member.
An exemplary semiconductor device 100 is shown in FIGS. 1A and 1B. The semiconductor device 100 includes trenches 110, 120 used to form conductive line interconnect structures and a contact opening 130 used to form a conductive plug interconnect structure defined in a base insulating layer 135. The contact opening 130 communicates with an underlying conductive feature 137 (e.g., metal line) formed in a previous layer of the semiconductor device 100. The trenches 110, 120 and contact opening 130 are lined with one or more barrier layers 140 and/or seed layers 150 and filled with a conductive layer 160 (e.g., a copper layer formed by electroplating). The seed layer 150 is shown using phantom lines as it is becomes homogenous with the conductive layer 160 during the plating process. A stop layer 170 is provided for protecting the base insulating layer 135 during a subsequent polishing process used to remove portions of the layers 140, 150 and conductive layer 160 extending beyond the trenches 110, 120 and contact opening 130, as shown in FIG. 1B.
The barrier layer 140 functions to inhibit electromigration of the copper fill layer in the trenches 110, 120 and contact opening 130. Electromigration is the displacement of metal ions in the copper layer due to the current flow in the line. The force of the propagating electrons is commonly referred to as xe2x80x9celectron wind.xe2x80x9d Over long periods of time, voids left behind by displaced ions accumulate. Eventually, an open circuit may occur, causing the semiconductor device to irreparably fail. Commonly used barrier layer materials include tantalum and tantalum nitride. An exemplary barrier layer 140 configuration includes a tantalum nitride layer lining the trenches 110 and contact opening 120 and a tantalum layer overlying the tantalum nitride layer.
The seed layer 150, typically comprising a deposited layer of copper or a copper alloy, is formed over the barrier layer 140 by a physical vapor deposition process (i.e., sputtering). The seed layer 150 is coupled to a voltage source during the subsequent plating of the conductive layer 160 to fill the trenches 110, 120 and contact opening 130 to complete the interconnect structures.
The conductive layer plating parameters (e.g., plating time, electrolyte temperature, and potential) affect the grain size of the conductive layer 160 and its integrity (i.e., whether seams or voids are present), which in turn affect the electrical parameters of the completed device. The plating parameters also affect the thickness of the conductive layer 160. If the conductive layer 160 is insufficiently thick, the trenches 110, 120 and contact openings 130 may be insufficiently filled. If the conductive layer 160 is thicker than necessary, the efficiency and cost-effectiveness of the processing line are reduced due waste from the additional conductive material and additional processing time and materials required to polish the conductive material extending beyond the trenches 110, 120 and contact openings 130.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a method for controlling a plating process. The method includes plating a process layer on a wafer in accordance with a recipe; measuring a thickness of the process layer; and determining at least one plating parameter of the recipe for subsequently formed process layers based on the measured thickness.
Another aspect of the present invention is seen in a processing line including a plating tool, a metrology tool, and a process controller. The plating tool is adapted to form a process layer on a wafer in accordance with a recipe. The metrology tool is adapted to measure a thickness of the process layer. The process controller is adapted to determine at least one plating parameter of the recipe for subsequently formed process layers based on the measured thickness.